Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance. For example, in silicon, hole mobility is enhanced when the channel film is under compressive stress in electrical current direction and/or under tensile stress in a direction normal of the silicon film, while the electron mobility is enhanced when the silicon film is under tensile stress in electrical current direction and/or under compressive stress in the direction normal of the silicon film. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-channel field effect transistor (p-FET) and/or an n-channel field effect transistor (n-FET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to cover the FET devices with compressively and/or tensilely stressed dielectric films, such as silicon nitride films. For example, U.S. Patent Application Publication No. 2003/0040158 published on Feb. 27, 2003 for “SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME” describes a semiconductor device that contains a first tensilely stressed nitride layer overlaying the channel region of an n-MOSFET, and a second compressively stressed nitride layer overlaying the channel region of a p-MOSFET, for respective application of tensile and compressive stresses to the n-MOSFET and p-MOSFET. However, such overlaying stressed nitride layers can only create a limited amount of stress in the channel regions of the MOSFET devices.
Recessed source and drain regions have been used in conjunction with the stressed nitride layers to improve the stress profile in the MOSFET channel region. Specifically, the source and drain regions of the MOSFET devices are etched back to form recesses with vertical sidewalls and a substantially flat bottom surface. A stressed nitride layer, which is formed not only on top of the MOSFET channel region but also in the source and drain recesses and over the vertical sidewalls of the MOSFET channel region, is significantly more effective in creating stress in the channel regions, in comparison with a similar nitride layer that is formed only on top of the MOSFET channel regions. However, such recessed source and drain regions with vertical sidewalls undercut the source and drain extension regions in the MOSFET, which leads to increased short channel effects, increased junction leakage, and deteriorated device performance.
There is therefore a need for improved MOSFET device structures with enhanced stress profile in the channel regions, without increasing the short channel effects and the junction leakage of the MOSFETs.